As may be appreciated by a person of ordinary skill in the art, the complex System-on-Chip (SoC) architectures developed in recent years may used with an ATPG tool to obtain the high quality production desired by the customer, and at the same time, to also obtain reduction of the generation time for the patterns. In other words, a designer of complex integrated circuit architecture, such as a SoC, may be assisted in testing activity by an ATPG tool that automatically generates the test patterns for the scan testing.
Scan testing may provide an efficient approach for testing the structural integrity of electronic devices, such as flip-flops and the logic gates among the circuit flip-flops, within a complex integrated circuit. Scan testing may not test integrated circuit-level functionality; however, test personnel may use scan testing to confirm that individual flip-flops and the logic gates among flip-flops within an integrated circuit are functioning properly.
Typically, complex integrated circuits may be designed and implemented as a series of interconnected functional blocks, each of which can be tested independently. Basic devices, such as flip-flops, can be connected together in a scan path to support scan testing. Flip-flops within a scan chain structure have their output connected to the input of a subsequent flip-flop. The first flip-flop within a scan path receives its input from an automated test unit through a test access port on the chip. The last flip-flop within a scan path provides its output to the automated test unit through a test access port.
Flip-flops may be taken from a library of basic cells available to the designer for building up a more complex chain structure. For a better understanding, analysis of a classical case illustrated in FIG. 1 concerning a standard library cell (LR1QLL), substantially an SR latch, follows below.
The test coverage that can be obtained using an ATPG tool with this kind of components is the following. Test coverage =0% (6 faults, 10 MOS), where 10 MOS is just an indication of the number of possible transistors forming the cell. The test coverage evaluations reported hereinbelow have been performed using a combinational ATPG algorithm because it may be commonly used to reduce the overall test pattern vectors and generation time. Using a sequential ATPG algorithm, of course, the coverage can be higher, but we may lose the advantage of reduced test vector generation and patterns count.
This means that with this approach, the cell 1 is described using a behavioral model, which may not be understood by the combinational ATPG tool algorithm that cannot detect faults. The problem in this respect may be the null coverage of the cell itself and also the problem of a low test coverage for the logic core observed by the SET-RESET inputs and a similar low test coverage for the logic core controlled by the output Q. So, the above basic cell may be considered by the ATPG tool as a black box, and for this reason, it is strongly suggested to avoid its use during the design activity.
Looking now at the CMOS schematic of the cell 1, it worthwhile to note that it is possible to describe that standard cell LR1QLL in more detail by making reference to FIG. 2, wherein a NAND-NAND structure is illustrated. As an alternative, a dual approach including a NOR-NOR structure may be taken in consideration.
So, referring to FIG. 2, a couple of two-input NAND gates 2 and 3 receive a Set or Reset command on a corresponding input terminal and present each respective output feedback cross-connected to the other input terminal of the other NAND gate. The output of the first NAND gate 2 is connected to the input of an inverter for providing at the inverter output the Q output value.
This representation of the LR1QLL cell illustrated in FIG. 2 may offer a set of faults, which is more realistic (more linked to the real physical defects) since the structural view is more equivalent to the transistor view.
In this specific case, the test coverage may be obtained using a combinational ATPG tool and is the following:test coverage=˜64% (22 faults, 10 MOS)
Also in this case, the test coverage is lower than the expected one. This may be due to the fact that the structure has a feedback loop (the cross connection between the NAND gates) that may prevent the ATPG tool from completely controlling/observing any node of the cell. As a consequence, the coverage of the input/output logic core may be lower than the target coverage.
A further possible approach is illustrated in FIG. 3, a structure 10 is provided by the prior art to overcome the problem of using a synchronous flip-flop with an asynchronous SET-RESET pin inserted in a scan chain. This approach comprises substituting the SR latch with a synchronous flip-flop having a set-reset asynchronous initialization. Moreover, this synchronous flip-flop 10 may use additional logic gates 6 and 7 to control the asynchronous SET-RESET pins from external pads or dedicated test modes during the ATPG control phase, since the inputs SET and RESET may be enabled in a mutually exclusive way.